The invention relates to the field of continuous-time integrated circuits filters. More particularly, it relates to an all NPN class-AB log-domain integrator.
Companding can be used to maintain reasonable dynamic range (DR) in integrated analog signal processors where the allowable voltage swings are limited by the low-voltage supply requirements of modem low-power applications. Syllabic companding is discussed in Y. Tsividis, xe2x80x9cExternally linear, time-invariant systems and their application to companding signal processors,xe2x80x9d IEEE Trans. Circuits Syst. II, vol. 44, no. 2, pp. 65-85, February 1997. As shown in FIG. 1(a) for the case of syllabic companding, the input signal is compressed before being processed, which ensures signal integrity over a large range of input levels. At the output, the signal is expanded to restore its dynamic range. This can result in a higher DR compared to conventional analog signal processors. Y. Tsividis et al. discuss this issue in xe2x80x9cCompanding in signal processing,xe2x80x9d Electronic Letters, vol. 26, no. 17, pp, 1331-1332, August 1990. Unlike the conventional processors) this does not come at the expense of increased power dissipation or chip area for a given bandwidth,
Log-domain filters, which constitute a special class of instantaneous companding signal processors are discussed in Y. Tsividis, xe2x80x9cExternally linear, time-invariant systems and their application to companding signal processors,xe2x80x9d IEEE Trans. Circuits Syst. II, vol. 44, no. 2, pp. 65-85, February 1997. They have already been used to realize programmable integrated filters reaching cutoff frequencies up to 220-435 MHz. For example, see M. N. El-Gamal and G. W. Roberts, xe2x80x9cVery high-frequency log-domain bandpass filters,xe2x80x9d IEEE Trans. Circuits Syst. II, vol. 45, no. 9, pp. 1188-1198, September 1998. and D. R. Frey, xe2x80x9cLog domain filtering for RF applications,xe2x80x9d IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1468-1475, October 1996. The power consumption of those filters is relatively high due to their 2.7-5 V power supplies, and the dynamic ranges are limited by class A operation. Two low-voltage class AB implementations have already been proposed. The first one is based on the bipolar integrator introduced by Seevinck (See E. Seevinck, xe2x80x9cCompanding current-mode integrator: A new circuit principle for continuous-time monolithic filters,xe2x80x9d Electronics Letters, vol. 26, no. 24, pp. 2046-2047, November 1990.), and the second one is the BiCMOS realization proposed by Punzenberger and Enz (See M. Punzenberger and C. C. Enz, xe2x80x9cA 1.2 V BiCMOS class AB log-domain filter,xe2x80x9d ISSCC Dig. Tech. Papers, pp. 56-57, February 1997.). Seevinck""s circuit is a good candidate for high-frequency applications, since it employs N-type devices only in the signal path. However, it needs a minimum supply voltage of ≈1.7 V, compared to the 1.2 V requirement of the BiCMOS circuit of Punzenberger and Enz.
There is therefore a need for a 1.2 V bipolar realization which does not employ PMOS or PNP devices in the signal path, making it suitable for VHF applications.
Accordingly, an object of the present invention is to provide very high-frequency (VHF) and low-voltage continuous-time filters with cutoff frequencies in the 30-100 MHz range, suitable for low-power applications with moderate linearity and SNR specifications (e.g. high-frequency digital communications), and requiring a wide frequency tuning range.
A further object of the present invention, is to propose a simple, common-mode interference-resistant, class AB log-domain integrator, suitable for implementation in low-cost bipolar processes.
Still another object of the present invention, is to make an integrator which is suitable for realizing low-voltage filters with reasonable linearity and SNR with compatible all-NPN low-distortion input and output interface stages.
A further object of the present invention is to realize high-frequency programmable filters.
Two variations of a continuous-time instantaneous companding filter are integrated in a 25 GHz bipolar process. Their xe2x88x923 dB frequencies are timable in the ranges of 1-30 MHz and 30-100 MHz. The dc gains are controllable up to 10 dB, The measured dynamic ranges for a 1% THD are 62.5 dB and 50 dB, for the 30 MHz and 100 MHz filters respectively. At maximum cutoff frequencies, the filters dissipate 6.5 mW from a 1.2 V supply.
The integrator preferably has the following characteristics:
1. It does not employ p-type transistors (e.g., PNP or PMOS transistors) in the signal path. This has the following two major advantages:
* The integrator maximum operating speed is not limited by the low-frequency p-type devices often provided in IC technologies. It is therefore suitable for high-frequency applications.
*Its implementation and use is not limited to the BiCMOS IC technologies or to the special bipolar IC technologies featuring high-quality PNP transistors. The integrator can therefore be used to implement filters in the many low-cost bipolar technologies available, giving it an edge over other circuits employing p-type devices in the signal path.
2. The integrator does not respond to a common-mode signal applied to its positive and negative input ports simultaneously. This makes it robust against interference, which is a very desirable feature in an IC environment, especially if digital circuitry share the same substrate with the integrator.
3. The integrator can operate from very low supply voltages, as low as 1.2 V. This makes it suitable for low-power applications (e.g. portable devices).
4. It is class-AB: It can therefore handle large signal currents despite of the limited supply voltage. This considerably extends its Dynamic Range (DR) and SNR.
5. It has a logarithmically nonlinear transfer function, making it suitable to be used in implementing the specific class of continuous-time filters called xe2x80x9clog-domain filtersxe2x80x9d. The latter are known to result in a high SNR compared to conventional filters.
The first two features discussed above (points 1, and 2.) are unique to the integrator circuit proposed in this invention. This gives it a substantial edge over the state-of-the-art BiCMOS, class-AB, 1.2 V integrator circuit. The latter is limited to the technology it can be used with, i.e. BiCMOS or high quality bipolar, in order to ensure high performance. It is also limited in operating speed: A prototype filter built using this integrator reached a maximum operating speed of only 1 MHz, compared to a similar prototype built with the proposed integrator, which reached a speed of 100 MHz. And finally, the conventional circuitry is more sensitive to interfering signals than the circuit proposed herein.
In addition to the integrator, a new input preprocessing stage is proposed, and a compatible output stage that complements it is also provided such that a complete filter can be implemented. The input stage converts a differential input signal into two xe2x80x9cstrictly positivexe2x80x9d complementary signals. Similar to the integrator, it uses a novel all-NPN circuit that can also operate from a supply voltage as low as 1.2 V.
Accordingly, a first broad aspect of the present invention is to provide a log-domain integrator. The log-domain integrator preferably comprises:
a positive compressed input voltage and a negative compressed input voltage;
a positive compressed output voltage and a negative compressed output voltage;
a ground and a reference voltage;
a first capacitor and a second capacitor;
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor;
a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a sixth current source, a seventh current source, an eighth current source, a ninth current source, a tenth current source, an eleventh current source, a twelfth current source;
wherein the first capacitor is connected between the negative compressed output voltage and the ground and the second capacitor is connected between the positive compressed output voltage and the ground;
wherein an output of the first current source is connected to a collector of the first transistor, a base of the second transistor, a base of the fifth transistor and a base of the first transistor;
wherein an output of the third current source is connected to a collector of the third transistor, a base of the fourth transistor and a base of the third transistor;
wherein an output of the fifth current source is connected to a collector of the fourth transistor, a base of the eleventh transistor and a base of the twelfth transistor;
wherein an output of the seventh current source is connected to a collector of the seventh transistor, a base of the fourteenth transistor and a base of the thirteenth transistor;
wherein an output of the eleventh current source is connected to a collector of the tenth transistor, a base of the tenth transistor, a base of the sixth transistor and a base of the ninth transistor;
wherein an output of the ninth current source is connected to a collector of the eighth transistor, a base of the seventh collector and a base of the eight collector;
wherein an input of the second current source is connected to the positive compressed input voltage and an emitter of the first transistor;
wherein an input of the twelfth current source is connected to the negative compressed input voltage and an emitter of the tenth transistor;
wherein an input of the fourth current source is connected to an emitter of the third transistor, a collector of the eleventh transistor, an input of the second capacitor, the positive compressed output voltage and an emitter of the second transistor;
wherein an input of the tenth current source is connected to an emitter of the eighth transistor, a collector of the fourteenth transistor, an input of the first capacitor, the negative compressed output voltage and an emitter of the ninth transistor;
wherein an input of the sixth current source is connected to an emitter of the fourth transistor, a collector of the twelfth transistor and an emitter of the sixth transistor;
wherein an input of the eighth current source is connected to an emitter of the seventh transistor, a collector of the thirteenth transistor and an emitter of the fifth transistor;
wherein the ground is connected to an output of the second current source, an emitter of the eleventh transistor, an emitter of the twelfth transistor, an emitter of the thirteenth transistor, an emitter of the fourteenth transistor, an output of the fourth current source, an output of the sixth current source, an output of the eighth current source, an output of the tenth current source, an output of the twelfth current source; and
wherein the reference voltage is connected to an input of the first current source., an input of the third current source, an input of the fifth current source, an input of the seventh current source, an input of the ninth current source, an input of the eleventh current source, a collector of the second transistor, a collector of the fifth transistor, a collector of the sixth transistor and a collector of the ninth transistor.
A second broad aspect of the present invention is to provide an input stage for a log-domain integrator comprising a positive half for generating a positive compressed input voltage and a negative half for generating a negative compressed input voltage, the positive and the negative half of the input stage each comprising:
a first do voltage;
a reference voltage;
a ground;
a linear Voltage-to-Current Converter;
one of a positive uncompressed input voltage and a negative uncompressed input voltage;
a fifteenth current source, a sixteenth current source, a seventeenth current source, an eighteenth current source, a nineteenth current source;
a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor;
wherein the first dc voltage, the reference voltage, the ground and the one of a positive uncompressed input voltage and a negative uncompressed input voltage are connected to the linear Voltage-to-Current Converter;
wherein a first output of the linear Voltage-to-Current Converter is connected to a base of the seventeenth transistor, a base of the twentieth transistor, a base of the twenty-third transistor;
wherein a second output of the linear Voltage-to-Current Converter is connected to an emitter of the sixteenth transistor, a collector of the seventeenth transistor;
wherein the first dc voltage is connected to a base of the nineteenth transistor and a base of the twenty-first transistor;
wherein the reference voltage is connected to a collector of the sixteenth transistor, an input of the fifteenth current source, a collector of the eighteenth transistor an input of the seventeenth current source, a collector of the twenty-second transistor, an input of the nineteenth current source;
wherein the ground is connected to an emitter of the seventeenth transistor, an emitter of the twentieth transistor, an emitter of the twenty-third transistor, an emitter of the twenty-fifth transistor, an output of the sixteenth current source, an output of the eighteenth current source;
wherein an output of the fifteenth current source is connected to a collector of the eighteenth transistor, a base of the eighteenth transistor and a base of the sixteenth transistor;
wherein an emitter of the eighteenth transistor is connected to an input of the sixteenth current source, an emitter of the eighteenth transistor and a collector of the twentieth transistor;
wherein an output of the seventeenth current source is connected to a collector of the twenty-first transistor and a base of the twenty-fifth transistor;
wherein an emitter of the twenty-first transistor is connected to an input of the eighteenth current source, an emitter of the twenty-second transistor, a collector of the twenty-third transistor;
wherein an output of the nineteenth current source is connected to a collector of the twenty-fourth transistor, a base of the twenty-fourth transistor and a base of the twenty-second transistor; and
wherein an emitter of the twenty-second transistor is connected to a corresponding one of the positive compressed input voltage and the negative compressed input voltage, respectively, and a collector of the twenty-fifth transistor.
Preferably, the linear Voltage-to-Current Converter comprises:
a thirteenth current source and a fourteenth current source;
a fifteenth transistor;
an input resistor;
wherein the first dc voltage is connected to a base of the fifteenth transistor;
wherein the input resistor is connected between an emitter of the fifteenth transistor and the one of the positive uncompressed input voltage and negative uncompressed input voltage;
wherein the thirteenth current source is connected between the reference voltage and a collector of the fifteenth transistor;
wherein the fourteenth current source is connected between the emitter of the fifteenth transistor and the ground;
wherein the first output of the linear Voltage-to-Current Converter is connected to the collector of the fifteenth transistor; and
wherein the second output of the linear Voltage-to-Current Converter is connected to the emitter of the fifteenth transistor.
A third broad aspect of the present invention is to provide an output post-processing stage. The output post-processing stage comprises a positive half for generating a positive uncompressed output voltage and a negative for generating a negative uncompressed output voltage. Each of these half comprises
a second dc voltage;
an output resistor;
a twentieth current source, a twenty-first current source, a twenty-second cument source;
a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor;
wherein the ground is connected to an output of the twenty-first current source, an emitter of the twenty-eighth transistor, an emitter of the thirtieth transistor;
wherein the reference voltage is connected to an input of the twentieth current source, a collector of the twenty-seventh transistor, an input of the output resistor and an input of the twenty-second current source;
wherein an output of the twentieth current source is connected to a collector of the twenty-sixth transistor, a base of the twenty-sixth transistor and a base of the twenty-seventh transistor;
wherein an emitter of the twenty-sixth transistor is connected to one of the positive compressed output voltage and the negative compressed output voltage and to an input of the twenty-first current source;
wherein an emitter of the twenty-seventh transistor is connected to an emitter of the twenty-ninth transistor and a collector of the twenty-eighth transistor;
wherein an output of the twenty-second current source is connected to a collector of the twenty-ninth transistor, a base of the thirtieth transistor and a base of the twenty-eighth transistor;
wherein the base of the twenty-ninth transistor is connected to the second dc voltage; and
wherein an output of the output resistor is connected to a collector of the thirtieth transistor and to a corresponding one of the uncompressed positive output voltage and the uncompressed negative output voltage, respectively.